The present invention relates generally to solid state memory devices, and more specifically, to optimizing the performance of solid state memory devices by partitioning.
The process of selecting which memory pages to displace from central storage and transfer to auxiliary storage is called page stealing, or page replacement. Pages of memory stored in real storage may need to be transferred to auxiliary storage depending on real storage usage patterns and the need for real storage by critical or high priority work. The pool of auxiliary storage available to the system may include a mixture of storage mediums, such as solid state memory device and direct access storage devices (DASD) storing for example, paging data sets.
The response time and performance consistency of a solid state memory device is impacted by previously run workloads in addition to a current workload, or workload of interest. Solid state memory devices, such as flash devices, include a set of access restrictions that force modern solid state memory controllers to employ features such as wear leveling to evenly utilize and wear over time. The introduction of the wear leveling style algorithms forces the solid state memory controllers to employ a mapping table to keep track of physical versus logical location of stored data. As the data is written to the device the mapping table is updated to keep track of where the new logical data is stored in the device based on the available free blocks in the solid state memory device. To gather a performance measurement for a specific workload, it takes time to stabilize the mapping table to the particular workload and hence it can require hours to get the device in the proper state. Furthermore as more workloads are generated for the solid state memory device, the performance results for the new workload are highly dependent on the previous activity to the device due to the preconditioning effect. This problem can make it very difficult to predict/understand device performance and response time.